2cb3d041cd
Move to kernel version 5.10 using source from the Yocto Project. 1. Add STX patches for kernel 5.10. 2. Support git source for linux-yocto. 3. Add build_srpm from build-tools/default_build_srpm and modified for git repo from yocto 4. Modify std and rt config files. 5. Build python-perf instead of python3-perf for std kernel. python-perf is needed by tuned-2.8.0-5.el7.noarch. 6. Modify rt spec to build out package kernel-rt-tools and kernel-rt-kvm. 7. Add kernel-5.10.30-x86_64-rt.config.tis_extra and kernel-5.10.30-x86_64.config.tis_extra 8. Add a dist field to avoid undesired rebuilds. 9. Ensure -unsigned package is populated Story: 2008921 Partial-Task: 42519 Signed-off-by: Jackie Huang <jackie.huang@windriver.com> Signed-off-by: Vefa Bicakci <vefa.bicakci@windriver.com> Signed-off-by: Jiping Ma <jiping.ma2@windriver.com> Change-Id: Id1f635302f265826f7ff2860a3bed4b7755b2888
80 lines
2.6 KiB
Diff
80 lines
2.6 KiB
Diff
From 4d58a9a618827e4410e3828b4deef5832a8576db Mon Sep 17 00:00:00 2001
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From: Jim Somerville <Jim.Somerville@windriver.com>
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Date: Wed, 29 Jan 2020 14:19:22 -0500
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Subject: [PATCH 07/10] Allow dmar quirks for broken bioses
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Problem:
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Broken bios creates inaccurate DMAR tables,
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reporting some bridges as having endpoint types.
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This causes IOMMU initialization to bail
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out early with an error code, the result of
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which is vfio not working correctly.
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This is seen on some Skylake based Wolfpass
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server platforms with up-to-date bios installed.
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Solution:
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Instead of just bailing out of IOMMU
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initialization when such a condition is found,
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we report it and continue. The IOMMU ends
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up successfully initialized anyway. We do this
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only on platforms that have the Skylake bridges
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where this issue has been seen.
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This change is inspired by a similar one posted by
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Lu Baolu of Intel Corp to lkml
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https://lkml.org/lkml/2019/12/24/15
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Signed-off-by: Jim Somerville <Jim.Somerville@windriver.com>
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Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
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---
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drivers/iommu/intel/dmar.c | 25 ++++++++++++++++++++++++-
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1 file changed, 24 insertions(+), 1 deletion(-)
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diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
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index 02e7c10a4224..7d423ac36a44 100644
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--- a/drivers/iommu/intel/dmar.c
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+++ b/drivers/iommu/intel/dmar.c
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@@ -66,6 +66,26 @@ static void free_iommu(struct intel_iommu *iommu);
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extern const struct iommu_ops intel_iommu_ops;
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+static int scope_mismatch_quirk;
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+static void quirk_dmar_scope_mismatch(struct pci_dev *dev)
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+{
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+ pci_info(dev, "scope mismatch ignored\n");
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+ scope_mismatch_quirk = 1;
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+}
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+
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+/*
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+ * We expect devices with endpoint scope to have normal PCI
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+ * headers, and devices with bridge scope to have bridge PCI
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+ * headers. However some PCI devices may be listed in the
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+ * DMAR table with bridge scope, even though they have a
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+ * normal PCI header and vice versa. We don't declare a
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+ * scope mismatch for the special cases below, even though
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+ * the bios creates broken tables.
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+ */
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+/* Sky Lake-E PCI Express Root Port A */
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+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2030,
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+ quirk_dmar_scope_mismatch);
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+
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static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
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{
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/*
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@@ -255,7 +275,10 @@ int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
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info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
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pr_warn("Device scope type does not match for %s\n",
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pci_name(info->dev));
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- return -EINVAL;
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+ if (!scope_mismatch_quirk)
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+ return -EINVAL;
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+ else
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+ pr_warn("but continuing anyway\n");
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}
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for_each_dev_scope(devices, devices_cnt, i, tmp)
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--
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2.29.2
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