853c60e2e8
This commit back ports the DPLL related commits from the upstream
kernel that are identified by Intel to provide the expected
SyncE/GNSS functionality.
There are totally 46 back ported commits included the four commits
I added are used to resolve the conflicts during back porting.
The 0046 patch is cherry picked from kernel-6.9.
The 0031-0045 patches are cherry picked from kernel-6.8.
The 0001-0030 patches are cherry picked from kernel-6.7.
We also change the in-tree ice driver version to 6.6.40-stx.2 from
6.6.40-stx.1.
* To fix the conflict of 91e43ca0090b ("ice: fix linking when
CONFIG_PTP_1588_CLOCK=n"), we cherry pick 12a5a28b565b
("ice: remove ICE_F_PTP_EXTTS feature flag") and 89776a6a702e
("ice: check netlist before enabling ICE_F_GNSS").
Adjust 12a5a28b565b because 0d1b22367ec2 ("ice: fix pin
assignment for E810-T without SMA control") already included
the part code of 12a5a28b565b.
https://git.yoctoproject.org/linux-yocto/commit/?id=0d1b22367ec2
* Cherry pick 7049fd5df7 ("netlink: specs: remove redundant type keys
from attributes in subsets") to fix the the conflict of c3c6ab95c397
("dpll: spec: add support for pin-dpll signal phase offset/adjust.")
* Cherry pick be16574609f1 ("ice: introduce hw->phy_model for handling
PTP PHY differences") to fix the confilict of 6db5f2cd9ebb ("ice:
dpll:fix output pin capabilities").
Verification:
- Build kernel and out of tree modules success for rt and std.
- Install success onto a All-in-One lab with rt kernel.
- Boot up successfully in the lab.
- interfaces are up and pass packets for rt and std.
- Check dmesg to see DDP package is loaded successfully and
the version is 1.3.36.0 for rt and std, that is same with the OOT
ice-1.14.9 driver.
- The SyncE/GNSS functionality tests were done by the network team.
Story: 2011056
Task: 50797
Change-Id: I715480681c7c43d53b0a0126b34135562e9d02a0
Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
106 lines
3.9 KiB
Diff
106 lines
3.9 KiB
Diff
From aebb7cbbcfce883a276aebfd7840d5297a471204 Mon Sep 17 00:00:00 2001
|
|
From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
|
|
Date: Mon, 18 Dec 2023 15:58:55 +0100
|
|
Subject: [PATCH 34/46] ice: dpll: fix phase offset value
|
|
|
|
Stop dividing the phase_offset value received from firmware. This fault
|
|
is present since the initial implementation.
|
|
The phase_offset value received from firmware is in 0.01ps resolution.
|
|
Dpll subsystem is using the value in 0.001ps, raw value is adjusted
|
|
before providing it to the user.
|
|
|
|
The user can observe the value of phase offset with response to
|
|
`pin-get` netlink message of dpll subsystem for an active pin:
|
|
$ ./tools/net/ynl/cli.py --spec Documentation/netlink/specs/dpll.yaml \
|
|
--do pin-get --json '{"id":2}'
|
|
|
|
Where example of correct response would be:
|
|
{'board-label': 'C827_0-RCLKA',
|
|
'capabilities': 6,
|
|
'clock-id': 4658613174691613800,
|
|
'frequency': 1953125,
|
|
'id': 2,
|
|
'module-name': 'ice',
|
|
'parent-device': [{'direction': 'input',
|
|
'parent-id': 6,
|
|
'phase-offset': -216839550,
|
|
'prio': 9,
|
|
'state': 'connected'},
|
|
{'direction': 'input',
|
|
'parent-id': 7,
|
|
'phase-offset': -42930,
|
|
'prio': 8,
|
|
'state': 'connected'}],
|
|
'phase-adjust': 0,
|
|
'phase-adjust-max': 16723,
|
|
'phase-adjust-min': -16723,
|
|
'type': 'mux'}
|
|
|
|
Provided phase-offset value (-42930) shall be divided by the user with
|
|
DPLL_PHASE_OFFSET_DIVIDER to get actual value of -42.930 ps.
|
|
|
|
Before the fix, the response was not correct:
|
|
{'board-label': 'C827_0-RCLKA',
|
|
'capabilities': 6,
|
|
'clock-id': 4658613174691613800,
|
|
'frequency': 1953125,
|
|
'id': 2,
|
|
'module-name': 'ice',
|
|
'parent-device': [{'direction': 'input',
|
|
'parent-id': 6,
|
|
'phase-offset': -216839,
|
|
'prio': 9,
|
|
'state': 'connected'},
|
|
{'direction': 'input',
|
|
'parent-id': 7,
|
|
'phase-offset': -42,
|
|
'prio': 8,
|
|
'state': 'connected'}],
|
|
'phase-adjust': 0,
|
|
'phase-adjust-max': 16723,
|
|
'phase-adjust-min': -16723,
|
|
'type': 'mux'}
|
|
|
|
Where phase-offset value (-42), after division
|
|
(DPLL_PHASE_OFFSET_DIVIDER) would be: -0.042 ps.
|
|
|
|
Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration")
|
|
Fixes: 90e1c90750d7 ("ice: dpll: implement phase related callbacks")
|
|
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
|
|
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
|
|
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
|
|
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
|
|
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
|
|
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
|
|
(cherry picked from commit 8278a6a43d030a3aa8d7768148e74844331e39e3)
|
|
Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
|
|
---
|
|
drivers/net/ethernet/intel/ice/ice_common.c | 4 +---
|
|
1 file changed, 1 insertion(+), 3 deletions(-)
|
|
|
|
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
|
|
index a1f1f037f327..7674267a2d90 100644
|
|
--- a/drivers/net/ethernet/intel/ice/ice_common.c
|
|
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
|
|
@@ -5303,7 +5303,6 @@ ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
|
|
u8 *eec_mode)
|
|
{
|
|
struct ice_aqc_get_cgu_dpll_status *cmd;
|
|
- const s64 nsec_per_psec = 1000LL;
|
|
struct ice_aq_desc desc;
|
|
int status;
|
|
|
|
@@ -5319,8 +5318,7 @@ ice_aq_get_cgu_dpll_status(struct ice_hw *hw, u8 dpll_num, u8 *ref_state,
|
|
*phase_offset = le32_to_cpu(cmd->phase_offset_h);
|
|
*phase_offset <<= 32;
|
|
*phase_offset += le32_to_cpu(cmd->phase_offset_l);
|
|
- *phase_offset = div64_s64(sign_extend64(*phase_offset, 47),
|
|
- nsec_per_psec);
|
|
+ *phase_offset = sign_extend64(*phase_offset, 47);
|
|
*eec_mode = cmd->eec_mode;
|
|
}
|
|
|
|
--
|
|
2.43.0
|
|
|