853c60e2e8
This commit back ports the DPLL related commits from the upstream
kernel that are identified by Intel to provide the expected
SyncE/GNSS functionality.
There are totally 46 back ported commits included the four commits
I added are used to resolve the conflicts during back porting.
The 0046 patch is cherry picked from kernel-6.9.
The 0031-0045 patches are cherry picked from kernel-6.8.
The 0001-0030 patches are cherry picked from kernel-6.7.
We also change the in-tree ice driver version to 6.6.40-stx.2 from
6.6.40-stx.1.
* To fix the conflict of 91e43ca0090b ("ice: fix linking when
CONFIG_PTP_1588_CLOCK=n"), we cherry pick 12a5a28b565b
("ice: remove ICE_F_PTP_EXTTS feature flag") and 89776a6a702e
("ice: check netlist before enabling ICE_F_GNSS").
Adjust 12a5a28b565b because 0d1b22367ec2 ("ice: fix pin
assignment for E810-T without SMA control") already included
the part code of 12a5a28b565b.
https://git.yoctoproject.org/linux-yocto/commit/?id=0d1b22367ec2
* Cherry pick 7049fd5df7 ("netlink: specs: remove redundant type keys
from attributes in subsets") to fix the the conflict of c3c6ab95c397
("dpll: spec: add support for pin-dpll signal phase offset/adjust.")
* Cherry pick be16574609f1 ("ice: introduce hw->phy_model for handling
PTP PHY differences") to fix the confilict of 6db5f2cd9ebb ("ice:
dpll:fix output pin capabilities").
Verification:
- Build kernel and out of tree modules success for rt and std.
- Install success onto a All-in-One lab with rt kernel.
- Boot up successfully in the lab.
- interfaces are up and pass packets for rt and std.
- Check dmesg to see DDP package is loaded successfully and
the version is 1.3.36.0 for rt and std, that is same with the OOT
ice-1.14.9 driver.
- The SyncE/GNSS functionality tests were done by the network team.
Story: 2011056
Task: 50797
Change-Id: I715480681c7c43d53b0a0126b34135562e9d02a0
Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
57 lines
2.1 KiB
Diff
57 lines
2.1 KiB
Diff
From 6bfe9392d6a26b04b24d310fc0e6342f139842eb Mon Sep 17 00:00:00 2001
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From: Jiri Pirko <jiri@nvidia.com>
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Date: Tue, 12 Dec 2023 16:06:05 +0100
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Subject: [PATCH 33/46] dpll: allocate pin ids in cycle
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Pin ID is just a number. Nobody should rely on a certain value, instead,
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user should use either pin-id-get op or RTNetlink to get it.
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Unify the pin ID allocation behavior with what there is already
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implemented for dpll devices.
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Signed-off-by: Jiri Pirko <jiri@nvidia.com>
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Link: https://lore.kernel.org/r/20231212150605.1141261-1-jiri@resnulli.us
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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(cherry picked from commit 97f265ef7f5b526b33d6030b2a1fc69a2259bf4a)
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Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
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---
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drivers/dpll/dpll_core.c | 8 +++++---
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1 file changed, 5 insertions(+), 3 deletions(-)
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diff --git a/drivers/dpll/dpll_core.c b/drivers/dpll/dpll_core.c
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index 3568149b9562..1eca8cc271f8 100644
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--- a/drivers/dpll/dpll_core.c
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+++ b/drivers/dpll/dpll_core.c
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@@ -22,7 +22,8 @@ DEFINE_MUTEX(dpll_lock);
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DEFINE_XARRAY_FLAGS(dpll_device_xa, XA_FLAGS_ALLOC);
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DEFINE_XARRAY_FLAGS(dpll_pin_xa, XA_FLAGS_ALLOC);
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-static u32 dpll_xa_id;
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+static u32 dpll_device_xa_id;
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+static u32 dpll_pin_xa_id;
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#define ASSERT_DPLL_REGISTERED(d) \
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WARN_ON_ONCE(!xa_get_mark(&dpll_device_xa, (d)->id, DPLL_REGISTERED))
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@@ -246,7 +247,7 @@ dpll_device_alloc(const u64 clock_id, u32 device_idx, struct module *module)
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dpll->clock_id = clock_id;
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dpll->module = module;
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ret = xa_alloc_cyclic(&dpll_device_xa, &dpll->id, dpll, xa_limit_32b,
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- &dpll_xa_id, GFP_KERNEL);
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+ &dpll_device_xa_id, GFP_KERNEL);
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if (ret < 0) {
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kfree(dpll);
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return ERR_PTR(ret);
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@@ -446,7 +447,8 @@ dpll_pin_alloc(u64 clock_id, u32 pin_idx, struct module *module,
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refcount_set(&pin->refcount, 1);
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xa_init_flags(&pin->dpll_refs, XA_FLAGS_ALLOC);
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xa_init_flags(&pin->parent_refs, XA_FLAGS_ALLOC);
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- ret = xa_alloc(&dpll_pin_xa, &pin->id, pin, xa_limit_16b, GFP_KERNEL);
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+ ret = xa_alloc_cyclic(&dpll_pin_xa, &pin->id, pin, xa_limit_32b,
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+ &dpll_pin_xa_id, GFP_KERNEL);
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if (ret)
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goto err;
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return pin;
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--
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2.43.0
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