853c60e2e8
This commit back ports the DPLL related commits from the upstream
kernel that are identified by Intel to provide the expected
SyncE/GNSS functionality.
There are totally 46 back ported commits included the four commits
I added are used to resolve the conflicts during back porting.
The 0046 patch is cherry picked from kernel-6.9.
The 0031-0045 patches are cherry picked from kernel-6.8.
The 0001-0030 patches are cherry picked from kernel-6.7.
We also change the in-tree ice driver version to 6.6.40-stx.2 from
6.6.40-stx.1.
* To fix the conflict of 91e43ca0090b ("ice: fix linking when
CONFIG_PTP_1588_CLOCK=n"), we cherry pick 12a5a28b565b
("ice: remove ICE_F_PTP_EXTTS feature flag") and 89776a6a702e
("ice: check netlist before enabling ICE_F_GNSS").
Adjust 12a5a28b565b because 0d1b22367ec2 ("ice: fix pin
assignment for E810-T without SMA control") already included
the part code of 12a5a28b565b.
https://git.yoctoproject.org/linux-yocto/commit/?id=0d1b22367ec2
* Cherry pick 7049fd5df7 ("netlink: specs: remove redundant type keys
from attributes in subsets") to fix the the conflict of c3c6ab95c397
("dpll: spec: add support for pin-dpll signal phase offset/adjust.")
* Cherry pick be16574609f1 ("ice: introduce hw->phy_model for handling
PTP PHY differences") to fix the confilict of 6db5f2cd9ebb ("ice:
dpll:fix output pin capabilities").
Verification:
- Build kernel and out of tree modules success for rt and std.
- Install success onto a All-in-One lab with rt kernel.
- Boot up successfully in the lab.
- interfaces are up and pass packets for rt and std.
- Check dmesg to see DDP package is loaded successfully and
the version is 1.3.36.0 for rt and std, that is same with the OOT
ice-1.14.9 driver.
- The SyncE/GNSS functionality tests were done by the network team.
Story: 2011056
Task: 50797
Change-Id: I715480681c7c43d53b0a0126b34135562e9d02a0
Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
108 lines
5.5 KiB
Diff
108 lines
5.5 KiB
Diff
From c6f3d22b1cdb4abcf53e2901974361bac7310635 Mon Sep 17 00:00:00 2001
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From: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
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Date: Wed, 11 Oct 2023 12:12:32 +0200
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Subject: [PATCH 20/46] dpll: docs: add support for pin signal phase
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offset/adjust
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Add documentation on:
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- measurement of phase of signal between pin and dpll
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- adjustment of pin signal phase
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Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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(cherry picked from commit 27ed30d1f861315719bd8c2b2e81576d71750331)
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Signed-off-by: Jiping Ma <jiping.ma2@windriver.com>
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---
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Documentation/driver-api/dpll.rst | 53 ++++++++++++++++++++++++++++++-
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1 file changed, 52 insertions(+), 1 deletion(-)
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diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
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index 69670deb8c4e..e3d593841aa7 100644
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--- a/Documentation/driver-api/dpll.rst
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+++ b/Documentation/driver-api/dpll.rst
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@@ -173,6 +173,47 @@ in order to configure active input of a MUX-type pin, the user needs to
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request desired pin state of the child pin on the parent pin,
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as described in the ``MUX-type pins`` chapter.
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+Phase offset measurement and adjustment
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+========================================
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+
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+Device may provide ability to measure a phase difference between signals
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+on a pin and its parent dpll device. If pin-dpll phase offset measurement
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+is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
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+attribute for each parent dpll device.
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+
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+Device may also provide ability to adjust a signal phase on a pin.
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+If pin phase adjustment is supported, minimal and maximal values that pin
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+handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
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+with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
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+attributes. Configured phase adjust value is provided with
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+``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
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+requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
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+
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+ =============================== ======================================
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+ ``DPLL_A_PIN_ID`` configured pin id
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+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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+ adjustment on parent dpll device
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+ ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
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+ configuration on given parent dpll
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+ device
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+ ``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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+ between a pin and parent dpll device
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+ =============================== ======================================
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+
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+All phase related values are provided in pico seconds, which represents
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+time difference between signals phase. The negative value means that
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+phase of signal on pin is earlier in time than dpll's signal. Positive
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+value means that phase of signal on pin is later in time than signal of
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+a dpll.
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+
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+Phase adjust (also min and max) values are integers, but measured phase
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+offset values are fractional with 3-digit decimal places and shell be
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+divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
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+modulo divided to get fractional part.
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+
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Configuration commands group
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============================
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@@ -263,6 +304,12 @@ according to attribute purpose.
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frequencies
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``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
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``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
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+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
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+ adjustment
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+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
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+ adjustment
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+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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+ adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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@@ -270,8 +317,10 @@ according to attribute purpose.
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dpll device
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``DPLL_A_PIN_STATE`` attr state of pin on the parent
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dpll device
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- ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
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+ ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
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parent dpll device
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+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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+ between a pin and parent dpll
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``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
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the pin is connected with
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``DPLL_A_PIN_PARENT_ID`` attr parent pin id
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@@ -284,6 +333,8 @@ according to attribute purpose.
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``DPLL_CMD_PIN_SET`` command to set pins configuration
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``DPLL_A_PIN_ID`` attr unique a pin ID
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``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
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+ ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
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+ adjustment on parent device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
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device configuration request
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``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
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--
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2.43.0
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