starlingx/kernel
Code Issues Proposed changes
kernel/kernel-std/debian/patches/0058-intel_idle-add-SPR-support.patch
M. Vefa Bicakci 0ee7813d66 kernel: Improve Sapphire Rapids CPU support 
This commit cherry-picks commits from the mainline kernel to improve
Sapphire Rapids CPU support in the following components of the StarlingX
kernel: intel_idle, perf/x86/RAPL and powercap, and perf/x86/cstate.
(RAPL stands for "Running Average Power Limit", which is a CPU feature
for measuring and limiting power consumption.)

These improvements are required to support a new power metrics
application in StarlingX, which is intended to work with Sapphire Rapids
CPUs: https://opendev.org/starlingx/app-power-metrics

The following commits are cherry-picked as part of this effort, in
chronological order, organized by component:

=> intel_idle
* commit 9edf3c0ffef0
  ("intel_idle: add SPR support")
  (v5.18-rc1~203^2~3^3~5)
* commit da0e58c038e6
  ("intel_idle: add 'preferred_cstates' module argument")
  (v5.18-rc1~203^2~3^3~4)
* commit 3a9cf77b60dc
  ("intel_idle: add core C6 optimization for SPR")
  (v5.18-rc1~203^2~3^3~3)
* commit 39c184a6a9a7
  ("intel_idle: Fix the 'preferred_cstates' module parameter")
  (v5.18-rc5~22^2^2~1)
* commit 7eac3bd38d18
  ("intel_idle: Fix SPR C6 optimization")
  (v5.18-rc5~22^2^2)
* commit 1548fac47a11
  ("intel_idle: make SPR C1 and C1E be independent")
  (v6.0-rc1~184^2~2^2^2)

=> perf/x86/rapl + powercap
* commit ffb20c2e52e8
  ("perf/x86/rapl: Add msr mask support")
  (v5.12-rc1~146^2~3)
* commit b6f78d3fba7f
  ("perf/x86/rapl: Only check lower 32bits for RAPL energy counters")
  (v5.12-rc1~146^2~2)
* commit 838342a6d6b7
  ("perf/x86/rapl: Fix psys-energy event on Intel SPR platform")
  (v5.12-rc1~146^2~1)
* commit 931da6a0de5d
  ("powercap: intel_rapl: support new layout of Psys PowerLimit Register
    on SPR")
  (v5.17-rc1~167^2^4^2~1)
* commit 80275ca9e525
  ("perf/x86/rapl: Use standard Energy Unit for SPR Dram RAPL domain")
  (v6.1-rc4~3^2~3)

=> perf/x86/cstate
* commit 87bf399f86ec
  ("perf/x86/cstate: Add ICELAKE_X and ICELAKE_D support")
  (v5.14-rc1~7^2~1)
* commit 528c9f1daf20
  ("perf/x86/cstate: Add SAPPHIRERAPIDS_X CPU support")
  (v5.18-rc4~3^2)

The set of commits listed above is a reduced version of a slightly
larger superset of commits we had originally considered for
cherry-picking. We opted for the commits listed above to limit potential
impact on the StarlingX kernel by focusing on Sapphire Rapids support
and direct dependencies only.

We should note that we encountered a number of merge conflicts while
cherry-picking these commits; however, none of the merge conflict
resolutions required significantly altering the modifications made by
the original commits. The individual patch files denote the nature of
the merge conflicts.

Verification:

* The kernel recipes and all kernel modules were built from scratch with
  this commit, using the following command in a StarlingX build
  environment:

  $ build-pkgs -c -p linux,linux-rt,bnxt-en,i40e,i40e-cvl-2.54,\
  i40e-cvl-4.10,iavf,iavf-cvl-2.54,iavf-cvl-4.10,ice,ice-cvl-2.54,\
  ice-cvl-4.10,igb-uio,iqvlinux,kmod-opae-fpga-driver,mlnx-ofed-kernel,\
  octeon-ep,qat1.7.l

  These packages were further packaged into a StarlingX (ostree) patch
  for easier deployment.

* An Ansible-bootstrapped low-latency All-in-One simplex StarlingX
  set-up was prepared on a server with a Sapphire Rapids CPU.

* The ostree patch was installed onto the server to start testing our
  changes. The kernel was confirmed to boot up as expected.

* We enabled RAPL Psys domain reporting the server's BIOS (originally
  disabled), and we also disabled the BIOS-enforced limit on the CPU
  *package* C-states (originally set to C0/C1).

* We forcibly removed the "intel_idle.max_cstate=0" kernel command line
  argument by modifying the sysinv daemon's Python source code on the
  server (with a systemd service that bind-mounts a replacement *.py
  file, to avoid another ostree patch). This was required to prevent the
  intel_idle driver from disabling itself, so that we could confirm the
  sanity of the cherry-picked commits.

* The following tests were carried out, first with the patched
  preempt-rt kernel, and next with the original unpatched preempt-rt
  kernel:

  * Confirm that the intel_idle CPU idling driver is active:
    $ cat /sys/devices/system/cpu/cpuidle/current_driver
  * Confirm the CPU idling state names and parameters:
    $ grep -s '^' \
    /sys/devices/system/cpu/cpu0/cpuidle/state[0-9]*/\
    {name,desc,time,latency,residency}
  * Confirm that the RAPL/powercap and C-state related performance
    monitor unit (PMU) counters are usable by the kernel and with perf:
    $ sudo perf list
  * Confirm that the CPU and package C-state residency counters are
    working:
    $ perf stat -a \
      -e cstate_core/c1-residency/ -e cstate_core/c6-residency/ \
      -e cstate_pkg/c2-residency/ -e cstate_pkg/c6-residency/ \
      -- sleep 5
  * Confirm that RAPL/powercap-related performance counters are working:
    $ perf stat -a \
      -e power/energy-pkg/ -e power/energy-ram/ -e power/energy-psys/ \
      -- sleep 5

  With the unpatched kernel, we observed that the intel_idle driver used
  CPU idling information exposed by the ACPI tables, with the following
  idle state names: POLL, C1_ACPI, C2_ACPI. With the patched kernel the
  C-state tables embedded in the intel_idle driver were used as
  expected, with the following idle state names: POLL, C1, C1E, C6.

  With the unpatched kernel, we observed that the CPU/package C-state
  residency counters were not detected, whereas they were detected with
  the patched kernel, as expected.

  With both the unpatched and the patched kernels, the RAPL/powercap
  related performance counters were detected. We observed that the units
  for the DRAM domain were incorrect for the unpatched kernel, which was
  expected due to the lack of commit 80275ca9e525 ("perf/x86/rapl: Use
  standard Energy Unit for SPR Dram RAPL domain").

* To confirm the sanity of our results acquired with the patched kernel
  in the previous step, we also carried out the following experiment
  with the v6.4.3-rt6 kernel available in the linux-yocto repository as
  commit 917d160a84f6 ("Merge branch 'v6.4/standard/base' into
  v6.4/standard/preempt-rt/base") in the "v6.4/standard/preempt-rt/base"
  branch.

  The "notification of death" StarlingX kernel patch was forward-ported
  to the v6.4.3-rt6 kernel and the "kernel.sched_nr_migrate" sysctl was
  reintroduced to make this kernel work with the aforementioned
  Ansible-bootstrapped StarlingX system.

  Furthermore, to ensure that the RAPL/powercap features are aligned to
  the most recent mainline kernel version, we cherry-picked the
  following commits from v6.5-rc1 onto the v6.4.3-rt6 kernel:
  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/log/?qt=range&q=44c026a73be8..49776c712eb6

  Afterwards, this v6.4.3-rt6-based test kernel was built and installed
  onto the test server, and test procedures discussed in the previous
  step were repeated.

  Compared to the patched StarlingX v5.10 kernel, we observed that the
  RAPL/powercap measurements were similar, and the CPU and package
  C-state residency counters were not extremely different with the
  v6.4.3-rt6-based test kernel.

* We should note that we have repeated tests with the patched StarlingX
  v5.10 kernel as well, but we did not reinstall the system to acquire a
  standard/non-low-latency set-up. Instead, we opted for running the
  following command, rebooting the system into the standard kernel,
  followed by repeating the test procedures, which had similar results.

  sudo grub-editenv /boot/1/kernel.env set kernel=vmlinuz-5.10.0-6-amd64

Acknowledgements:

* Thanks to Alyson Deives Pereira for his extensive help in pruning the
  commits that we had originally thought of cherry-picking with this
  commit.

* Thanks to Mark Asselstine for his advice on the second phase of the
  commit pruning activity.

Story: 2010773
Task: 48449

Change-Id: Ibe6bff65e8a415ac027a5d493a0e65fe58c9e344
Signed-off-by: M. Vefa Bicakci <vefa.bicakci@windriver.com>
2023-07-24 13:44:38 +00:00

123 lines
4.5 KiB
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From 865f32679b6bbf92ebf4e0a74c36170c21c4250e Mon Sep 17 00:00:00 2001
From: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Date: Wed, 2 Mar 2022 10:15:58 +0200
Subject: [PATCH] intel_idle: add SPR support
Add Sapphire Rapids Xeon support.
Up until very recently, the C1 and C1E C-states were independent, but this
has changed in some new chips, including Sapphire Rapids Xeon (SPR). In these
chips the C1 and C1E states cannot be enabled at the same time. The "C1E
promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit.
Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR.
1. If C1E promotion bit is disabled.
a. C1 requests end up with C1 C-state.
b. C1E requests end up with C1E C-state.
2. If C1E promotion bit is enabled.
a. C1 requests end up with C1E C-state.
b. C1E requests end up with C1E C-state.
Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon.
1. If C1E promotion bit is disabled.
a. C1 requests end up with C1 C-state.
b. C1E requests end up with C1 C-state.
2. If C1E promotion bit is enabled.
a. C1 requests end up with C1E C-state.
b. C1E requests end up with C1E C-state.
Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was
exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot be
enabled at the same time.
This patch adds both C1 and C1E states. However, C1E is marked as with the
"CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by
default. The C1E promotion bit will be cleared, which means that by default
only C1 and C6 will be registered on SPR.
The next patch will add an option for enabling C1E and disabling C1 on SPR.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit 9edf3c0ffef0ec1bed8300315852b5c6a0997130)
[mvb: Fix merge conflict caused by a lack of IceLake-D support in
StarlingX.]
Signed-off-by: M. Vefa Bicakci <vefa.bicakci@windriver.com>
---
drivers/idle/intel_idle.c | 47 +++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index b92b032fb6d1..7694d852b49d 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -778,6 +778,46 @@ static struct cpuidle_state icx_cstates[] __initdata = {
.enter = NULL }
};
+/*
+ * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vice
+ * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in
+ * MSR_IA32_POWER_CTL. But in this case there effectively no C1, because C1
+ * requests are promoted to C1E. If the "C1E promotion" bit is cleared, then
+ * both C1 and C1E requests end up with C1, so there is effectively no C1E.
+ *
+ * By default we enable C1 and disable C1E by marking it with
+ * 'CPUIDLE_FLAG_UNUSABLE'.
+ */
+static struct cpuidle_state spr_cstates[] __initdata = {
+ {
+ .name = "C1",
+ .desc = "MWAIT 0x00",
+ .flags = MWAIT2flg(0x00),
+ .exit_latency = 1,
+ .target_residency = 1,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C1E",
+ .desc = "MWAIT 0x01",
+ .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE | \
+ CPUIDLE_FLAG_UNUSABLE,
+ .exit_latency = 2,
+ .target_residency = 4,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .name = "C6",
+ .desc = "MWAIT 0x20",
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 290,
+ .target_residency = 800,
+ .enter = &intel_idle,
+ .enter_s2idle = intel_idle_s2idle, },
+ {
+ .enter = NULL }
+};
+
static struct cpuidle_state atom_cstates[] __initdata = {
{
.name = "C1E",
@@ -1088,6 +1128,12 @@ static const struct idle_cpu idle_cpu_icx __initconst = {
.use_acpi = true,
};
+static const struct idle_cpu idle_cpu_spr __initconst = {
+ .state_table = spr_cstates,
+ .disable_promotion_to_c1e = true,
+ .use_acpi = true,
+};
+
static const struct idle_cpu idle_cpu_avn __initconst = {
.state_table = avn_cstates,
.disable_promotion_to_c1e = true,
@@ -1143,6 +1189,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
+ X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
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