d642a320e3
This commit adds Sapphire Rapids 5G Instruction Set Architecture
(SPR-5G-ISA) support to the CentOS-based StarlingX kernel. This involves
AVX512-FP16 instructions, but note that these instructions are not
directly used by the kernel.
The benefits for StarlingX users are the ability to enumerate CPUs'
AVX512-FP16 capabilities, and the ability to start KVM-based virtual
machines that can make use of the capabilities in question. (Please note
that supporting AVX512-FP16 with KVM virtual machines requires patching
StarlingX's qemu-kvm-ev package in addition to this commit, as well.)
The cherry-picked commits were acquired from the v5.11 kernel release,
and all of them applied cleanly. The only change to the patches involved
the third patch, which was modified to remove a reference to a CPU
feature (X86_FEATURE_VM_PAGE_FLUSH) support for which is not provided by
StarlingX's v5.10 kernel baseline.
Test plan:
- CentOS-based StarlingX
- Standard and preempt-rt kernels and all out-of-tree kernel modules
were successfully built using a monolithic build procedure.
- An ISO image was successfully built with this change.
- The changes were confirmed to not negatively affect installation and
Ansible boot-strap procedures in All-in-One Simplex virtual machines
using standard and low-latency profiles.
- Using a Sapphire Rapids-based server in All-in-One Simplex
configuration, the aforementioned ISO image was installed and
Ansible-bootstrapped, and the enumeration of the "avx512_fp16" CPU
feature in /proc/cpuinfo was verified with the low-latency and
standard kernels.
- Debian-based StarlingX
- An ISO image was successfully built (in an incremental manner) with
this change.
- The changes were confirmed to not negatively affect installation and
Ansible boot-strap procedures in All-in-One Simplex virtual machines
using standard and low-latency profiles. (Due to time constraints,
Debian-based StarlingX tests were carried out with virtual machines
only.)
Story: 2010247
Task: 46073
Change-Id: I430de20651b6c4a0aa0d854d295b1760cb7b889c
Signed-off-by: M. Vefa Bicakci <vefa.bicakci@windriver.com>
52 lines
2.3 KiB
Diff
52 lines
2.3 KiB
Diff
From 79f57d6d0f55cb6402cb445da438fee8d9133352 Mon Sep 17 00:00:00 2001
|
|
From: Arnaldo Carvalho de Melo <acme@redhat.com>
|
|
Date: Mon, 21 Dec 2020 09:04:54 -0300
|
|
Subject: [PATCH] tools headers cpufeatures: Sync with the kernel sources
|
|
|
|
To pick the changes in:
|
|
|
|
69372cf01290b958 ("x86/cpu: Add VM page flush MSR availablility as a CPUID feature")
|
|
e1b35da5e624f8b0 ("x86: Enumerate AVX512 FP16 CPUID feature flag")
|
|
|
|
That causes only these 'perf bench' objects to rebuild:
|
|
|
|
CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
|
|
CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o
|
|
|
|
And addresses these perf build warnings:
|
|
|
|
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
|
|
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
|
|
|
|
Cc: Adrian Hunter <adrian.hunter@intel.com>
|
|
Cc: Ian Rogers <irogers@google.com>
|
|
Cc: Jiri Olsa <jolsa@kernel.org>
|
|
Cc: Kyung Min Park <kyung.min.park@intel.com>
|
|
Cc: Namhyung Kim <namhyung@kernel.org>
|
|
Cc: Paolo Bonzini <pbonzini@redhat.com>
|
|
Cc: Tom Lendacky <thomas.lendacky@amd.com>
|
|
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
|
(cherry picked from commit 7f3905f00a2025591a6883ee6880f928029b4d96)
|
|
[mvb: Remove X86_FEATURE_VM_PAGE_FLUSH from this commit as that CPU
|
|
feature constant is not provided by StarlingX's v5.10 baseline.]
|
|
Signed-off-by: M. Vefa Bicakci <vefa.bicakci@windriver.com>
|
|
---
|
|
tools/arch/x86/include/asm/cpufeatures.h | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
|
|
index b58730cc12e8..d7accc927691 100644
|
|
--- a/tools/arch/x86/include/asm/cpufeatures.h
|
|
+++ b/tools/arch/x86/include/asm/cpufeatures.h
|
|
@@ -374,6 +374,7 @@
|
|
#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
|
|
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
|
|
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
|
|
+#define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */
|
|
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
|
|
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
|
|
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
|
|
--
|
|
2.29.2
|
|
|